USB TYPE-C

TYPE-C，C是接口物理形式的版本号

在电源上来说，属于供电设备( TYPE-C中称为SRC即SOURCE)，在数据传输上来说，属于HOST(TYPE-C中称为DFP即DownStream Face port), 反过来，属于用电方(TYPE-C中的 SNK即SINK)，数据传输上属于Slaver(TYPE-C中的UFP即UPStream Face port)

第一、电能传输功能差异。USB Typc-C的特点在于，所有支持TYPE-C接口标准的设备都可以通过接口规范中的CC引脚的电平来向连接的另一方宣称自己占用VBUS的意愿，较强意愿的一方最终向VBUS输出电压和电流，另一方则接受VBUS总线的供电。为了能够更方面的使用这个总线定义。Type-C接口芯片(例如LDR6013)，一般把从电源特性上把设备分为五种角色：SRC,TRY.SRC,DRP,TRY.SNK,SNK，这五种角色占用VBUS总线的意愿依次递减。其中SRC相当于适配器，会持续想要向VBUS输出电压，TRY.SRC相当于移动电源，只有当遇上适配器时，才放弃输出VBUS，DRP相当于笔记本电脑，可以接受适配器提供的电能进行充电，也可以输出电能给手机充电。TRY.SNK相当于手机，正常情况下，期待对方给自己供电，但是遇上比自己还弱的设备，例如U盘时，也勉为其难的向对方输出， SNK是不对外输出电能的，一般为弱电池设备，或者无电池设备，例如u盘，鼠标，蓝牙耳机。这个就是所谓的CC LOGIC。在CC LOGIC中，最难做的是移动电源。因为用户要求移动电源要给一切能够接受充电的设备进行充电，包括笔记本电脑。而市场上有部分笔记本电脑的CC逻辑是TRY.SRC,例如Chromebook,华为的Matebook等。于是，就出现了市面上部分移动电源无法充笔记本电脑的问题，经常出现笔记本电脑反过来往移动电源充电。电子工程师在移动电源设计阶段就遇到了这个问题，并为之困扰。后来找到了一颗LDR6013，终于解决了这个问题。

第二、数据传输功能差异。传统的USB接口，一般内部只有一个业务处理单元，例如USB3.0处理芯片，USB2.0处理芯片等。而TYPE-C接口，允许最多三组业务处理单元，可以通过对模拟开关的控制，同时支持两组数据传输业务(一组USB3.0,一组USB2.0)加一组HDMI信号传输业务。或者是三组的任意组合。所以，一个TYPEC接口，最多可以支持三组传输加一组供电，共4种功能。

第三、电能及数据传输性能差异。USB TYPE-C支持正反插，由于正反两面一共具有四组电源和地，在功率支持上有了大幅度的提升，最高支持20V，5A 100瓦传输能力。将带来传统用电器供电的革命。同时还兼具有公头和母座两层完整的金属保护壳EMC防护，令传输速度可以上升到最高40G。

母座上有24根信号，其中电源和地占据了8根，用于提升电流传输能力，剩下16个，用于传输USB2.0的两组信号是交叉相连的，去掉重复的两个，一共是14个信号。包括我们所熟悉的2组共8根可用于传输usb3数据的RXx和TXx，USB2.0数据信号D+，D-和SBU1，SBU2，CC1，CC2。 其中SBU1，SBU2，CC1，CC2是传统的USB接口所没有的信号。CC是USB TYPE-C接口的灵魂所在，承载了TYPE-C连接过程中的传输方向确认和正反插确认功能，以及USB PD BCM码信号传输功能，实现负载的功能配置。两根线CC线，当其中一根CC作为TYPE-C接口的配置信号时，另一个CC则作为电缆上EMARKER芯片的供电电源。剩下的SBU1和SBU2为辅助信号，在不同的应用场景具有不同的用途。例如在ALT MODE 模式下进行DP信号传输时，作为音频传输通道，在进入TYPE-C模拟音频耳机附件模式，则作为麦克风信号传输通道。

那么，被提及最多的正反插，究竟是怎么实现的呢?秘诀在于CC公头上。让我们来看CC公头的结构。

对比母座接线图，我们可以看出，公头只有一个CC，另外一个CC变成了VCONN，于是，当公头插入母座的时候，公头上的CC可能跟母座上的CC1连在一起，也可能跟母座的CC2连接在一起，分别对应着正插和反插两种情况。母座上需要用一颗芯片来检测是CC1建立了连接，还是CC2建立了连接，从而控制设备内部的SWITCH，来正确的适配数据传输，或者是音视频传输的信号对应关系。

USB BC 1.2 vs PD 1.0 vs PD 2.0 vs PD 3.0 vs PD 3.0 PPS vs USB PD 3.1 – Specs Sheet

For some purposes, these voltages may not be ideal, in which case the Programmable Power Supply (PPS) or Adjustable Voltage Supply (AVS) modes may be more suitable. The PPS mode can be used with SPR, following the rough voltage levels of the latter, but allowing for the voltage to be adjusted between 3.3 V and the SPR voltage level plus 1 or 2 V, in steps of 20 mV.

AVS mode does basically the same thing as PPS, only starting from 15 V as the lowest voltage level, ranging up to any of the three EPR voltages in steps of 100 mV. Which of these voltages are available in PPS or AVS mode works the same as with regular fixed voltage usage, in that the USB-PD controller determines the limits based on the detected hardware.

PORT Configuration

• As stated in the USB Type-C™ and USB Power Delivery specifications, any port can be assigned a data role (DFP or UFP) and a power role (source, sink or DRP): 
• a Source is a USB Power Delivery Port supplying power; on an attach event, it assumes the DFP and VCONN Source roles • a Sink is a USB Power Delivery Port consuming power; on an attach event, it assumes the UFP role 
• a Dual-Role Power Port (DRP) supports both Source and Sink roles

Source Port (provider) This port is able to supply power over VBUS (5 V to 20 V and up to 5 A), and must assert a pull-up resistor (Rp) resistor on the configuration channel (CC) pins

Sink Port (consumer) This port is able to consume power over VBUS (from 5 V to 20 V and up to 5 A) and must assert a pull-down resistor (Rd) on the CC pins

Dual-Role Power (DRP) Port A Dual-Role Power Port (DRP) can operate as either a fixed Source or a Sink port, or alternate between the two roles through the USB PD Power Role Swap command.

USB Type-C and Power Delivery architecture

Device Policy Manager (DPM) The Device Policy Manager (DPM) deals with the USB Power Delivery resources used by one or more ports on the basis of the local device policy. It interacts with the Policy Engine and USB-C Port control blocks of the device to implement the local policies for each port.

Policy Engine (PE) The Policy Engine (PE) interacts directly with the DPM to determine which local policy to apply. Its role is to drive the message sequences according to the sent message and its expected response. It allows power negotiation by establishing an explicit contract for power exchange. The acceptance or the refusal of a request depends on the response of the DPM with respect to a specific power profile. The PE also handles the flow of vendor defined messages, allowing the discovery, entry and exit of modes supported by the provider and consumer sides.

Protocol layer (PRL) The protocol layer drives message construction, transmission, reception and acknowledgment. It allows the monitoring of message flows and the detection of communication errors. The protocol layer builds and sends messages according to indications from the Policy Engine, and forwards responses to those messages back to the Policy Engine.

Physical layer (PHY) The physical layer is responsible for sending and receiving messages across the CC wire. It is responsible for managing data over the wire, avoiding collisions and detecting errors in the messages through a Cyclic Redundancy Check (CRC).

CC pins: port termination characteristics

The Configuration Channel (CC) pins are used in the discovery, configuration and management of connection across a USB Type-C™ cable, as well as a communication channel for the PHY layer of the USB Power Delivery. There are two CC pins in each receptacle, but only one is connected through the cable to establish communication. The other pin can be re-assigned as the VCONN pin for powering electronics in the USB Type-C™ plug of electronically-marked cables. Specific Rd and Rp resistor values connected to CC pins allow single role or dual role system configuration. The attachment and orientation detection operations are carried out through CC lines through these resistors:

• a source must assert Rp pull-up resistors on both CC pins

• a sink must assert Rd pull-down resistors on both CC pins

• a DRP port is equipped with both Rp pull-up resistors and Rd pull-down resistors on its CC pins and is able to dynamically assert the appropriate resistors when the role is fixed by the application according to the operated power role

• a full-featured USB Type-C cable must assert Ra pull-down resistors on the VCONN pin

 Power negotiation

PD Power Profile

SOP is used for messages between Source and Sink.

SOP’ is used for messages close to Vconn Source (for supplying power to e-Markers in cables),

and SOP” is used for messages delivered to the cable’s far-end e-Marker.

1. For the maximum output of 140W, the following conditions must be met:

• SPR Fixed PDO： 5V@3A~5A 、9V@3A~5A、15@3A~5A 、20V@5A
• EPR Fixed PDO： 28V@5A
• AVS APDO 15V~28V@140W

EPR PDO includes:

1. Fixed PDO: Constant voltage output. In EPR mode, Fixed PDO refers to the specification with a voltage >20V, including 28V, 36V and 48V.
2. AVS (Adjustable Voltage Supply) APDO: In EPR mode, the voltage output can be adjusted within a certain range, from a minimum of 15V to a maximum of 28V, 36V and 48V, depending on the wattage (Table 2).
   AVS is similar to PPS in terms of function, but the difference is that AVS does not support Current Limit operation, and the output voltage is adjusted in a unit step of 100mV (20mV for PPS).

Table 1. Specification Supporting EPR Product Power Supply (Refer to PD 3.1 Spec)

Table 2. AVS Voltage Range (Source : PD 3.1 Spec)

The following two examples are offered to help readers understand Table 2 (above).

1. For the maximum output of 140W, the following conditions must be met:

• SPR Fixed PDO： 5V@3A~5A 、9V@3A~5A、15@3A~5A 、20V@5A
• EPR Fixed PDO： 28V@5A
• AVS APDO 15V~28V@140W

2. For an output of 144W, the following conditions must be met (see the wattage range in the second column of Table 1):

• SPR Fixed PDO： 5V@3A~5A、9V@3A~5A、15@3A~5A、20V@5A
• EPR Fixed PDO： 28V@5A、36V@4A
• AVS APDO： 15V~36V@144W
  * The notation of AVS APDO is different from SPR Fixed PDO or EPR Fixed PDO. This is because the AVS operating current is limited by the wattage and varies with the current operating voltage. Since the current is not a fixed value, the wattage should be referred to instead of the current. See Table 3( below), where the maximum current is expressed in wattage.

Table 3. AVS APDO format (Source: PD 3.1 Spec)

In the 144W example, the current conditions of AVS APDO under the operating voltage of 28.8V~36V can be easily understood by referring to Figure 1 (below). The blue area in the figure represents the AVS operable range, which can be divided into two zones:

1. Zone A, marked in yellow, can operate within the voltage range of 5A and under, but not exceeding the maximum wattage (See the first description in Table 1 – 15V~28.8V@5A).
2. Zone B, marked in green, is subject to the wattage limit, and the operating current depends on the voltage, so it is expressed by the formula – 28.8V~36V@ (144/AVS voltage) A.

Figure 1. Diagram of AVS Power Supply Mode

It is worth noting that the areas marked N/A in Table 1 are strictly not supported. Specifically, products below 140W do not support 36V and 48V, and products below 180W do not support 48V.

Another product design is a Shared Capacity Charger, which means that the power supply wattage on the product is shared. When part of the wattage has been used, the wattage available to the remaining ports is the total wattage minus the portion used. Subject to allocation and the actual available wattage at this time, this is called Equivalent PDP Rating. Refer to the table below (Table 4) for setting conditions.

Table 4. Conditions Supporting EPR product in Shared Capacity Power Supply Mode (Refer to PD 3.1 Spec)

Take the following product design as an example: The maximum total output wattage is 250W, and when the 2 ports are used alone they can support up to 160W respectively:

• If used independently, the specification is (5V@3A~5A, 9V@3A~5A, 15@3A~5A, 20V@5A, 28V@5A, 36V@4.44A, 15V~36V@160W).
• When one port is used 100W, the Equivalent PDP Rating of the other port is 150W, the power supply conditions are as follows: 5V@3A~5A, 9V@3A~5A, 15@3A~5A, 20V@5A, 28V@5A, 36V@4.16A, and 15V~36V@150W.

EPR_Source_Capabilities

The power supply capability is displayed in Source_Capabilities, and the same concept is imported into EPR mode. EPR_Source_Capabilities has been added to PD 3.1 Spec to support and display the specifications of EPR power supply products.

As shown in the following diagram taken from the PD 3.1 Spec, the first 7 groups of Data Objects are filled with SPR PDO content, which must be the same as those in Source_Capabilities. If the SPR PDO has less than 7 groups, then 0 shall be used.

EPR PDO content is entered from Group 8 to Group 13, in sequence from low Fixed PDO voltage to high Fixed PDO voltage, followed by a group of AVS APDO.

Figure 2. EPR_Source_Capabilities format (Source: PD 3.1 Spec)

EPR mode process

Before entering EPR mode for power supply, Source/Sink needs to establish an Explicit PD Contract. During this, both parties confirm whether they support EPR mode in the Source Capabilities and Request Messages respectively. This is used as a reference to check the capabilities of both parties before entering EPR mode.

Before entering EPR mode, a communication and check process is required. The steps are as follows:

• Enter EPR Mode

1. Sink sends EPR_Mode message, where the Data Object is set as Enter, indicating that communication in EPR mode is required. The EPR_Mode message depends on the content (see Figure 3), which indicates different purposes.
2. Source checks and confirms that both parties support EPR mode, and the current state is able to support EPR mode power supply. It sends an EPR_Mode message set to Enter Acknowledged, indicating that the current state of Source allows entry to EPR mode
3. In products with wires, Source must confirm that the wire used can support EPR mode. It also sends a Discover ID Request to confirm that the wire can support a maximum voltage of 50V and a maximum current of 5A.
4. If all of the above are OK, Source will send an EPR_Mode message set to Enter Succeeded in the Data Object to Sink, and then successfully enter EPR mode and move to the next step, which is “PD Negotiation.”

Figure 3. EPR Mode DO Message (Source: PD 3.1 Spec)

Figure 4. EPR Mode Data Objects (EPRMDO) (Source: PD 3.1 Spec)

PD Negotiate in EPR Mode

1. Source sends EPR_Source_Capabilities to announce the power supply capability in EPR mode
2. Sink selects PDO according to requirements, fills in the EPR_Request and sends it to Source
3. When Source confirms that the requirements can be met, it will send back an Accept signal and, after adjusting the power supply state, transmit PS_RDY to complete this communication

In EPR mode, Source detects the CC state. If it is idle for too long, Source will initiate a Hard Reset. This results in an interruption of EPR mode, so Sink needs to transmit an EPR_KeepAlive message at specified intervals to maintain EPR mode. When Source receives this message, it responds to GoodCRC and EPR_KeepAlive_Ack and resets the timing.

Exit EPR Mode

Source/Sink may want to return to SPR mode due to various factors. However, before this, the voltage must first be lowered to a constant of at least 20V, which can be achieved by the following two methods:

1. Source sends EPR_Source_Capabilities for re-communication, with the notification that EPR PDO is not included
2. Sink sends EPR_Request and makes clear in the content that only SPR PDO is required. i.e. that EPR PDO is not included

               After either of these two actions are completed, the voltage should drop to 20V or lower. At this time, either Source or Sink can initiate EPR_ Mode and set the Data Object in the message to Exit, indicating that it will exit EPR mode. When either party sends this message, Source needs to send Source Capabilities within the tFirstSourceCap parameter time to re-establish the PD Contract and return to SPR mode.

Figure 5. Example of the EPR Mode Process (GoodCRC in the middle omitted)

Type-C Cable and Connector update

The “Universal Serial Bus Type-C Cable and Connector Specification” has been updated to Version 2.1, with the goal of adding EPR functions at all supported speeds.

Table 5. Cable Categories (Source: Type-C Cable and Connector Spec)

EPR Cable

• EPR cables must contain an E-Marker to clarify this capability.
• The E-Marker must be set to EPR Mode Capable and provide notification that it supports 50V and 5A.
• The minimum working voltage of EPR cables must be at least 53.65V.

According to some experiments, the Vbus pin can become damaged under the following conditions:

• Source: When the current load is suddenly removed, and the voltage changes rapidly.
• Sink: When the Vbus pin at the receiving end is in a high voltage state for a long time.
• Cable：

1. If the Vbus continues to oscillate (i.e within microseconds).
2. When the current load is suddenly removed within 0.1-1 microseconds, leading to a sudden drop in IR voltage.

原文链接：https://www.cnblogs.com/zjbfvfv/p/16138776.html